The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package to which a fan-out packaging technique is applied and to a method of manufacturing the same.
Electronic products are required to process large amounts of data while being miniaturized. Accordingly, there is a growing need to increase the integration of semiconductor devices used in such electronic products. To this end, semiconductor chips are being stacked and electrically connected to one another using various packaging technologies. For example, semiconductor packages containing chips are stacked and electrically connected by wires in a process known as a wire bonding process. However, the use of a wire bonding process in this type of application requires the overall semiconductor package be rather thick, and it is difficult to stack more than 4 layers, and T-topology may appear when a redistribution layer is used for more than 2 loads. Recently, panel level package (PLP) and wafer level package (WLP) technologies for increasing integration and reducing unit cost are being researched and developed.